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Parasitic-Aware Optimization of CMOS RF Circuits 🔍
David J. Allstot, Kiyong Choi, Jinho Park (auth.) Springer Science & Business Media, 1 edition, February 2003
English [en] · PDF · 9.2MB · 2003 · 📘 Book (non-fiction) · 🚀/lgli/scihub/upload/zlib · Save
description
In the arena of parasitic-aware design of CMOS RF circuits, efforts are aimed at the realization of true single-chip radios with few, if any, off-chip components. The parasitic-aware RF circuit synthesis techniques described in this book effectively address critical problems in this field.
Alternative filename
scihub/10.1007/b101853.pdf
Alternative filename
zlib/Engineering/David J. Allstot, Kiyong Choi, Jinho Park/Parasitic-Aware Optimization of CMOS RF Circuits_26395970.pdf
Alternative author
by David J. Allstot, Kiyong Choi, Jinho Park
Alternative author
David James Allstot; Kiyong Choi; Jinho Park
Alternative author
Allstot, David J., Park, Jinho, Kiyong Choi
Alternative author
David J. Allstot; Jinho Park; Kiyong Choi
Alternative publisher
Kluwer Academic Publishers
Alternative edition
United States, United States of America
Alternative edition
Springer Nature, Boston, 2003
Alternative edition
Boston, Massachusetts, 2003
metadata comments
sm39596523
metadata comments
producers:
Acrobat Distiller 6.0 (Windows)
metadata comments
Includes bibliographical references and index.
Alternative description
In the arena of Parasitic-Aware Design of CMOS RF Circuits, efforts are aimed at the realization of true single-chip radios with few, if any, off-chip components. Ironically, the on-chip passive components required for RF integration pose miore serious challenges to SOC integration than the active CMOS and BJT devices. This is not surprising since modern digital IC designs are dominated as much, or more, by interconnectg characteristics than by active device properties. In any event, the co-integration of active and passive devices in RFIC design represents a serious design problem and an even more daunting manufacturing challenge. If conventional mixed-signal design techniques are employed, parasitics associated with passive elements (resistors, capacitors, inductors, transformers, pads, etc.) and the package effectively de-tune RF circuits rendering them sub-optimal or virtually useless. Hence, dealing with parasitics in an effective way as part of the design process is an essential emerging methodology in modern SOC design. The parasitic-aware RF circuit synthesis techinques described in this book effectively address this critical problem.
Erscheinungsdatum: 28.02.2003
Alternative description
Aimed at the goal of true single-chip wireless devices, this book provides analyses of challenges involved with the co-integration of active and passive devices in RFIC design, and how modeling parasitic properties during the design phase can minimize undesirable effects such as the de-tuning of RF circuits. The book begins with background on "parasitic-aware" optimization, and then covers topics including monolithic inductors; simulated annealing with tunneling process; particle swarm optimization; and optimization of CMOS low-noise amps, mixers, RF power amps, and CMOS ultra-wideband amps. Annotation (c)2003 Book News, Inc., Portland, OR (booknews.com)
Alternative description
<p>aimed At The Goal Of True Single-chip Wireless Devices, This Book Provides Analyses Of Challenges Involved With The Co-integration Of Active And Passive Devices In Rfic Design, And How Modeling Parasitic Properties During The Design Phase Can Minimize Undesirable Effects Such As The De-tuning Of Rf Circuits. The Book Begins With Background On Parasitic-aware Optimization, And Then Covers Topics Including Monolithic Inductors; Simulated Annealing With Tunneling Process; Particle Swarm Optimization; And Optimization Of Cmos Low-noise Amps, Mixers, Rf Power Amps, And Cmos Ultra-wideband Amps. Annotation (c)2003 Book News, Inc., Portland, Or</p>
Alternative description
In the near future, people's daily activities will be dominated with portable wireless devices.
date open sourced
2015-06-04
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